The present invention relates generally to gate arrays, more particularly to an electrical distribution system for gate arrays exposed to radiation environments, and specifically to gate arrays that may experience short term exposure to a high level of ionizing radiation. This type of exposure is referred to as dose rate or prompt dose.
It is well known to use standardized gate arrays to construct semi-custom integrated circuits. A gate array formed in a semiconductor die or chip requires an electrical power distribution or power bussing system to provide the necessary voltage levels to circuits integrated in the die. This electrical distribution system typically takes the form of a conductive paths for providing a positive voltage, for example 3 volts and a conductive path for providing a reference voltage, for example ground. For gate array applications not subject to radiation environments the electrical distribution system is designed to meet various requirements and to provide the proper voltage level throughout the entire chip. To meet this requirement considerations is given to factors such a resistive voltage drops along the bus and electromigration. For non radiation applications calculations for power bussing systems that consider the maximum current requirements and include appropriate safety factors can be made and these calculations along with knowledge of the integrated circuit layout details can be used to determine the conductor sizing and spacing in a relatively straight forward fashion.
The design of a power bussing system for a gate array that will be subjected to a high level of ionizing radiation requires that additional factors be considered. The photocurrents generated in PN junctions of semiconductors subjected to ionizing radiation such as gamma or X-rays cause soft error rates in SRAM circuits, storage devices and failures in ROM. The photocurrent effects are global, i.e., every device on a chip served by the same power bussing is simultaneously affected by the photocurrents. One of the most common problems that results from the dose rate event is the reduction in the differential power supply voltage, that is a reduction in the difference between the positive voltage, for example VDD and the reference voltage, for example VSS. This reduction of course occurs across individual devices, for example, transistors, across circuit paths in the chip and in the package and across bonding wires connecting the chip to the package. The cause of this reduction in the differential power supply voltage is the droop of the local VDD voltage and the rise of the local VSS voltage due to the photocurrent contributions of all circuit components generated through the finite resistance and inductance of the power bussing and chip package. The result of this reduction is to lower the transient radiation upset threshold voltage. In addition the reduction can permit latch-up and burn out a device at sufficiently high dose rates.
The details of the power supply bussing of the prior art can be explained with reference to FIG. 1 which shows a greatly simplified top view drawing of a power bussing arrangement for a portion of a radiation resistant chip as found in the prior art. Chip 2 includes a Vdd buss 4 and a Vss buss 6, each of which extend around the perimeter 9 of chip 2 and have chip bond pad 5 and chip bond pad 7 for connection to power and ground, respectively. Chip 2 is typically housed in a package 8 which includes a method for bringing power and ground to chip 2, for example, package Vdd bond pad 10 and package Vss bond pad 12 which receive power and ground through conductors (not shown) located within package 8. Individual pairs of power and ground busses are located within the chip. For example, second metal Vdd bus 16 and second metal Vss buss 18 comprise one pair and second metal Vdd Buss 20 and second metal Vss buss 22 comprise another pair. Several additional Vdd and Vss pairs would exist if a more complete top view of chip 2 were shown in FIG. 1. Within chip 2, first metal Vdd busses 24 are connected to Vdd buss 16 by vias 26 and extend horizontally. Transistors 28, for example, p-channel transistors, would be connected to first metal buss 24. First metal Vss busses 30 are connected to Vss buss 18 by vias 32 and extend horizontally. Transistors 34, for example, n-channel transistors, would be connected to first metal buss 30.
FIG. 1a shows a cross-sectional view of a first metal buss 24, via 26 and second metal buss 16.
When a dose rate event occurs electron hole pairs are formed at PN junctions and photocurrents result. Electrons are attracted to the Vdd voltage and flow, for example from chip areas to first metal busses 24 through vias 26 and Vdd busses 16 to Vdd pad 5. A voltage due to the IR drop and the Ldi/dt drop causes the voltage at first metal buss 24 to be reduced. Holes are attracted to the Vss voltage and flow, for example from chip areas to first metal busses 30 through vias 32 and Vdd busses 18 to Vss pad 7. A voltage due to the IR drop and the Ldi/dt drop causes the voltage at first metal buss 30 to rise. Thus the differential voltage between first metal Vdd buss 24 and first metal Vss buss 30 is reduced.
Using the approach of the prior art, an increased dose rate requirement means that the increased size or quantity of power buss pairs requires more chip space, which in turn means loss in gate count and/or routing resources which, in turn, can result in the original circuit design no longer fitting on the gate array.
Thus a need exists for an electrical power distribution system that will meet the requirement of higher dose rates without significantly increasing the power bussing network.